· Highly experienced ASIC Backend Engineer with over 3 years in digital backend design, specializing in synthesizing RTL, timing convergence, and managing the complete backend flow for successful tape-outs.
· Adept at floorplanning, physical synthesis, clock tree and clock gating design, power analysis, routing, layout integration, and physical verification.
· Possesses strong expertise in low power design and deep sub-micron technology (22nm or below), and is proficient with EDA tools such as ICC2, Innovus, Primetime, Calibre, and Redhawk.
· Skilled in scripting languages like Perl, TCL, and Shell, with a solid educational foundation in Electrical Engineering (BSEE, MSEE preferred).
· Known for being a self-motivated team player with a strong commitment to delivering high-quality ASIC designs.
